1. Field of the Invention
The present invention relates to a semiconductor device, particularly, to a MIS (Metal Insulator Semiconductor) type FET (Field Effect Transistor) having a silicide film in an upper portion of the source-drain diffusion layers.
2. Description of the Related Art
In recent years, an elevated source-drain technology is proposed in order to suppress the problem in respect of a junction leak defect of a transistor.
The MOS type FET device having an elevated source-drain structure is manufactured by the process shown in, for example, FIGS. 1A to 1E.
In the first step, an isolation region 12 consisting of a silicon oxide film is formed in a semiconductor substrate 11, as shown in FIG. 1A. A gate structure is formed on the semiconductor substrate 11 by laminating a gate insulating film 13, a gate electrode 14, and a gate electrode cap silicon oxide film 15 on the semiconductor substrate 11 in the order mentioned. Then, an impurity is implanted into the semiconductor substrate 11 with the gate structure used as a mask so as to form a first diffusion region 16 on the semiconductor substrate 11.
In the next step, a sidewall insulating film 17 is formed on the side surface of the gate electrode 14, as shown in FIG. 1B, followed by forming a mono-crystalline semiconductor film 18 on the first diffusion region 16, as shown in FIG. 1C. The mono-crystalline semiconductor film 18 can be formed by a selective epitaxial CVD technology using silicon or silicon-germanium.
After formation of the semiconductor film 18, the gate electrode cap silicon oxide film 15 is removed, followed by implanting an impurity into the semiconductor substrate. As a result, a second diffusion region 19 is formed within the semiconductor substrate 11. In this step, the impurity is also introduced into the gate electrode 14 and the mono-crystalline semiconductor film 18.
In the next step, a metal film (not shown) for forming a silicide film is deposited on the entire surface of the resultant structure, followed by applying a heat treatment to the metal film. Finally, the excess portion of the metal film is selectively removed so as to form a silicide film 20 on the surfaces of the gate electrode 14 and the mono-crystalline semiconductor film 18, as shown in FIG. 1E.
As shown in the drawing, the source-drain diffusion layers are constructed to have surfaces elevated by the selective epitaxial growth technology of silicon. As a result, it is possible to increase the margin relative to the junction leak current generation.
However, in order to form a silicon film uniformly while maintaining the selectivity on the silicon layer and on the insulating film, it is necessary for the selective epitaxial growth process of silicon to be carried out under the condition of high temperatures not lower than 850° C. It should be noted that, if such a high temperature process is carried out, the first diffusion region 15, which is required to maintain a shallow junction depth of the diffusion layer, is expanded deep into the semiconductor substrate 11 so as to lead to deterioration of the device characteristics.
In order to avoid the inconvenience described above, proposed is a technology that the junction depth of the source-drain regions are made equal to or shallower than the junction depth of the diffusion region.
Also proposed is to form a polycrystalline silicon (polysilicon) layer between a SiGe film and a CoSi2 layer in the silicide gate so as to lower the resistance. However, in the case of forming a silicide film on the SiGe film, it is difficult to suppress the deterioration of the morphology.